Electro-optical devices based on Liquid Crystals (LC) make use of variable properties of LCs upon absence or presence of an electric field to control their optical operation, typically by selectively allowing (by becoming transparent) or preventing (by becoming opaque) incident light transmission such as in the case of LC cells used in display (LCD) devices, or by changing their refractive properties such as in the case of LC cells used as Tunable-focus LC Lens (TLCL) devices. TLCLs are manufactured employing wafer fabrication as cells (dies) on wafers.
During mass manufacturing processes of such electro-optical devices, defects are likely to be induced (develop) on some of these devices (dies prior to singulation), which could adversely affect their operation when in use (after singulation). As part of quality control procedures, all or at least representative samples of the fabricated devices (dies) are being subjected to optical (functional) testing to ensure proper operation prior to making them available for end use.
Turning to FIGS. 1a and 1b, there is schematically illustrated a typical known arrangement designated at 10 for testing a single electro-optical device (after singulation). Liquid crystal cell 12 has first and second planar driving electrodes (layers) 14, 16 provided on first and second transparent glass substrates 18, 20 and being disposed in a predetermined spatial relationship with respect to one another. Planar driving electrode layers 14, 16 are delicate, in the order of microns thick. For testing purposes, a prior art technique includes mechanically placing test probes on each driving electrode 14, 16 associated with each individual LC cell die. Driving electrodes 14, 16 are connected to output terminals 22, 22′ of an external electrical voltage source 24, an electrical arrangement 10 including first and second testing electrodes (probes) 26, 28 connected to electrical voltage source 24 through respective external lines 27, 29 and connectors 30, 30′ directly making physical electrical contact with driving electrode (layers) 14, 16, respectively. Upon application of a (driving) voltage of a predetermined value across driving electrodes 14, 16, the LC cell 12 is caused to operate by changing its light transmission or refractive properties in accordance with the electrical field generated (applied), whose intensity can be expressed by the well known capacitance relation:E=VLC/d 
wherein V_LC is the voltage value applied across the LC cell and d is the distance separating the driving electrodes (layers) 14, 16 of the LC cell. An induced optical property change can be sensed through the use of an appropriate optical analyzer, allowing identification of any defective portion of the liquid crystal device.
Turning now to FIGS. 2a and 2b, there is schematically illustrated a typical known arrangement 10″ which is similar to the arrangement 10 described above in view of FIGS. 1a and 1b, wherein the electro-optical device under test is a single TLCL including one or more optional dielectric layers 32, such as field modulating hidden layers, weakly conductive layers or supporting substrates for optically active layers.
Such a prior art technique requires the fabrication such an LC optical device to have progressed to an advanced state past singulation or is applicable to low yield singly fabricated LC optical devices. Moreover, the required physical contact with the delicate micron thick driving electrode layers 14, 16 is inefficient. It can be appreciated, in view of the foregoing examples, that the known testing technique according to the prior art makes use of testing electrodes directly making physical, electrical contact with delicate driving electrode layers in order to apply the desired voltage to the electro-optical device under test exposing such TLCL devices to potential damage such as scratching during testing. To be applicable, such technique requires the availability of direct contact locations on the substrates, which must be externally accessible and not hidden for testing during manufacture. Whenever, a single electro-optical device 12′, or a multiple electro-optical device unit 11′, such as illustrated in FIG. 3 does not provide such externally accessible electrical contact locations connected to respective driving electrodes, operational testing prior to singulation employing the presently known technique exhibits an important limitation which renders such testing a very difficult task, if not infeasible.
Referring now to FIG. 4 there is shown another prior art arrangement 10′ based on the same known principle, for testing in parallel the performance of a multiple electro-optical device unit 11, such as a wafer, formed of first and second substrates 18′, 20′ and including a two-dimensional array of electro-optical devices such as LC cells 12′ built in the wafer. It is appreciated that driving electrodes layers 14′, 16′ have an extent limited to single LC cells 12′. An grid of “scribe line” (kerf) areas extends between adjacent LC optical device dies 12′ containing a network lines 27′, 29′ for evaluating the fabrication process. For parallel test purposes, a plurality of line pairs 27′, 29′, each connected to driving electrodes 14′, 16′ of a single LC cell 12′, are connected to output terminals 22, 22′ of external electrical voltage source 24. A plurality of pairs of first and second test electrodes 26, 28, connected to electrical voltage source 24 through external lines 27, 29, are used to make direct physical contact via connectors 30, 30′ with respective network lines 27′, 29′ and indirectly to make electrical contact with driving electrodes 14′, 16′.
For example, unpublished U.S. patent application Ser. No. 07/933,325, filed Aug. 21, 1992 by Rostoker, et al., entitled “Methods For Die Burn-In”, serving as parent for U.S. continuation application Ser. No. 08/370,565 of same title issued as U.S. Pat. No. 5,489,538 on Feb. 6, 1996, describes such a technique for burning-in semiconductor circuit chips, as opposed to liquid crystal optical device dies, prior to dicing (on the wafer) in accordance with which a common network of power and ground conductors in the scribe lines are provided. The power and ground lines connect to all dies on a wafer. The power and ground lines simply power up all devices for static burn-in. Built-in semiconductor circuit chip self test (self-starting, signal-generating) circuitry on each die provides signals on power up to exercise some of the functionality of the chip.
Similarly, U.S. Pat. No. 5,389,556 entitled “Individually Powering-Up Unsingulated Dies On A Wafer” issued Feb. 14, 1995 to Rostoker, et al. describes testing a multitude of unsingulated semiconductor circuit chips (dies) on a wafer by individually powered up using various “electronic mechanisms” on the wafer, and connecting the electronic mechanisms to the individual dies by conductive lines on the wafer. Rostoker '556 proposes placing a number of conductors in the scribe line areas on a wafer, including: at least one power line and at least one ground line for powering up the dies for testing; a multitude of probe lines and a multitude of sense lines for implementing a cross-check type testing methodology; and preferably, redundant power and ground lines, to provide coverage in the event of an open line.
As is well known in the art, scribe lines areas, and anything contained within them, will be destroyed when the dies are singulated from the wafer. Such networks of power lines, sense lines, probe lines and conductors are therefore sacrificial.
In the wafer fabrication field there is a pressure to maximize the useful or productive area of a wafer to increase yield and reduce production costs which dictates that scribe line area be kept as small as possible. Dies are desired to be laid out on a wafer in a pattern that is packed as tightly as possible. Desirable scribe line widths include only those large enough to ensure that the dies can be separated without damage to the device area of the dies.